1. Field of the Invention
The present invention relates to a method of driving a liquid crystal display device and, in particular, to a method of driving an active-matrix liquid crystal display device utilizing a two-terminal element as a switching element of a pixel.
2. Related Art
An active-matrix type of liquid crystal display device provides a higher contrast than a conventional passive type of device, so they are becoming increasingly common in various manufacturing fields that use displays. Two types of active elements are used: two-terminal type and three-electrode type. The two-terminal type is considered to be superior from the economical point of view.
Some of the two-terminal type of active elements that are used are metal-insulator-metal (MIM) elements, ring diodes, and varistors.
In general, a two-terminal type of active element utilized in an active-matrix type of liquid crystal display device has the I-V characteristic shown in FIG. 3. In other words, it uses a switching function caused by a non-linear characteristic of current with respect to applied voltage, to charge and discharge an effective electrical charge applied to the picture element.
The configuration of an active-matrix liquid crystal display device using a two-terminal type of active element is shown in FIG. 1. In this figure, reference number 101 denotes a column drive circuit (X driver) that drives column electrodes of a liquid crystal panel 115, and 102 denotes a row drive circuit (Y driver) that drives row electrodes thereof.
In the X driver 101, reference number 104 denotes an AC video generation circuit which accepts a video signal (P) input, and generates an AC video signal in synchronization with an AC inversion signal FRX. Reference number 103 denotes a shift register that is activated by a shift start signal DX, performs a shift operation in synchronism with a shift clock signal XSCL, and sequentially generates a sampling signal Sm. Reference number 105 denotes a first analog switch that samples the AC video signal generated from the AC video generation circuit 104 by the sampling signal Sm and holds it in a capacitor 106. The capacitor 106 is a first sample-and-hold capacitor. Reference number 107 denotes a second analog switch that transfers the sampled video signal held in the capacitor 106 to another capacitor 108 by a latch pulse LP. The capacitor 108 is a second sample-and-hold capacitor. Reference number 109 denotes a buffer amplifier that drives a column electrode Xm on the basis of the video signal held in the capacitor 108.
Within the Y driver 102, reference number 110 denotes an inverter that uses Vp and -Vp as power sources and generates a selection voltage signal Vs in synchronization with an AC inversion signal FRY. Reference number 111 denotes a shift register that is activated by a shift start signal DY, performs a shift operation in synchronism with a shift clock signal YSCL, and generates a selection signal Cn. Reference number 112 denotes a power source selection switch for one cell of a drive circuit for a row electrode Yn.
The internal configuration of the selection switch 112 is shown in FIG. 2. The AC inversion signal FRY and selection signal Cn are input to shift register latches which consists of NOR gates 201 and 202. An output from the NOR gate 201 and an inverted signal obtained by an inverter 203 from the selection signal Cn are both input to AND gates 204 and 205, and outputs therefrom are input to gate electrodes of analog switches 207 and 208, respectively. The selection signal Cn is also input to a gate electrode of an analog switch 206. The selection voltage signal Vs and power sources -Va and Va are input to source electrodes of the analog switches 206 to 208, respectively, drain electrodes of the analog switches 206 to 208 are connected in common, and a signal Yn (a signal for driving the row electrode Yn) is output therefrom.
Reference number 115 denotes a liquid crystal panel. Column electrodes Xm and row electrodes Yn are formed on the respective substrates of the liquid crystal panel 115, and at each intersection thereof a non-linear element 114 and a liquid crystal layer 113 are arranged in series to form a pixel. In this case, voltages applied to the liquid crystal layer 113 and the non-linear element 114 are Vm and Vl, with respect to the row electrode.
The non-linear element 114 has the current-voltage characteristic shown in FIG. 3. As can be seen from this figure, when the applied voltage is small, the current is extremely small; when the applied voltage is large, the current characteristic increases steeply.
The operation of the example of a prior art liquid crystal display device shown in FIG. 1 and FIG. 2 will now be described with reference to the timing charts of FIG. 4 to FIG. 6.
As shown in FIG. 4, the video signal (P) is inverted in synchronization with the AC inversion signal FRX (when FRX=1, the phase of (P) is positive; when FRX=0, the phase of (P) is negative) to obtain an AC video signal 104. In this case, Va is the 100% white level of the positive-phase video signal and the 0% white level (pedestal level) of the negative-phase video signal, and -Va is the 0% white level (pedestal level) of the positive-phase video signal and the 100% white level of the negative-phase video signal. The shift start signal DY of the Y driver is sequentially transferred by the shift clock signal YSCL to generate selection signals C1, C2, C3 . . . Cn, . . . The latch pulse LP and the shift start signal DX of the X driver are input every horizontal scanning period.
An enlarged view of a specific horizontal scanning period is shown at the bottom of FIG. 4. The latch pulse LP is positioned roughly at the synchronization portion of the video signal, and it transfers the video signal that was sampled and held in the capacitor 106 during the previous horizontal scanning period to the capacitor 108. The shift start signal DX is positioned roughly at the start of the video signal portion in one horizontal scanning period, and it is transferred by the shift clock signal XSCL to generate sampling signals S1, S2, S3 . . . Sm, . . . For example, the nth video signal 104 sampled by sampling signal Sm (the sampling position marked by a circle (.smallcircle.) in the FIG. 4) is output to the column electrode Xm at the timing of the (n+1)th video signal after one horizontal scanning period.
FIG. 5 is a timing chart of the components shown in FIG. 2. According to logic combination of the selection signal Cn and the AC inversion signal FRY (in this prior art example, a common AC inversion signal is input to both the X driver and the Y driver--in other words, FRX=FRY), the outputs of the shift register latches 201 and 202 are made to repeatedly invert between 1 (Cn=1, FRY=0) and 0 (Cn=1, FRY=1). When Cn=1, Yn outputs the selection voltage signal Vs (which is at -Vp when FRY=1 or Vp when FRY=0); when Cn=0 (called the non-selection period or hold period), Yn outputs a voltage corresponding to the polarity at the immediately previous selection (when Cn=1)--i.e., it is Va after a positive (Vp) selection or -Va after a negative (-Vp) selection.
FIG. 6 is a timing chart of the column electrode signal Xm and the row electrode signal Yn, together with a difference signal Xm-Yn thereof. Video data which corresponds to the mth column in the horizontal direction along the liquid crystal panel 115 is sequentially sampled by the AC video signal, and is output as the line electrode signal Xm. The row electrode signal Yn outputs the selection voltage signal Vs during a selection period Ts, and a non-selection potential Va or -Va during a non-selection period Th. The non-selection potential after a selection at positive potential Vp is Va, and that after a selection at negative potential -Vp is -Va.
The difference signal Xm-Yn is shown as a solid line in the signal chart at the bottom of FIG. 6. In this case, the broken-line track is that of the potential at the connection between-the liquid crystal layer 113 and the non-linear element 114. Since a large voltage is applied to the non-linear element 114 during the selection period Ts, the current flowing therein is large, as can be understood from the I-V characteristic of FIG. 3, and the liquid crystal layer 113 is charged thereby. The amount of this electric charge is controlled by the amplitude of Xm-Yn during the selection period Ts or by the level of the column electrode signal Xm, i.e., by the level of sampling by the AC video signal 104. As described above, by changing the non-selection potential to match the polarity of the preceding selection potential, the signal level of the difference signal Xm-Yn is made positive in the non-selection period after a positive-polarity selection period, and negative in the non-selection period after a negative-polarity selection period. Therefore, the voltage applied to the non-linear element 114 in each non-selection period becomes small and thus it becomes difficult for the charge on the liquid crystal layer 113 to leak through the non-linear element 114 during the selection period. The effective voltage applied to the liquid crystal layer 113 is proportional to the shaded area in FIG. 6, and thus in effect depends on the level of the sampled video signal. The liquid crystal layer 113 controls the amount of light that passes through it in correspondence with the effective voltage applied to it, and thus a predetermined image is displayed on the liquid crystal panel 115.
However, two-terminal non-linear elements, especially MIM and metal-insulator-semiconductor (MIS) elements, experience a characteristic shift, as will be described below. As shown in FIG. 7, I-V1 denotes the initial current-voltage characteristic of a two-terminal non-linear element and I-V2 denotes the same characteristic that has shifted while a voltage was continuously applied to the element (refer to: E. Mizobata et al., SID91 Digest, p. 226 (1991)). In comparison with the I-V1 characteristic, the I-V2 characteristic shows that resistance increases when the voltage is high, which means that a reduced charge is written to the liquid crystal layer during the selection period. When the voltage is low, there is very little difference in resistance, which means that there is little difference in charge held in the liquid crystal layer during the non-selection period. It is known that this I-V characteristic shift saturates with voltage applied to the liquid crystal layer.
The effect of this I-V characteristic shift on the display will now be described with reference to the display of a white window against a black background, as shown in FIG. 8. Consider a pixel P1 that is displaying black at the intersection of column electrode Xm1 and row electrode Yn, and a pixel P2 that is displaying white at the intersection of column electrode Xm2 and row electrode Yn. When the entire screen changes to an an intermediate display, as shown in FIG. 9, the previous window display remains as an afterimage. In other words, pixel P1 ends up lighter than pixel P2. The reason for this will now be explained with reference to FIG. 10. Xm1-Yn denotes the signal applied to pixel P1 and Xm2-Yn denotes the signal applied to pixel P2. A voltage VmsW applied to the non-linear element of pixel P2 during the selection period Ts of the white-display period is greater than a voltage VmsB applied to the non-linear element of pixel P1 of the black-display period. Thus, the non-linear element of pixel P2 has a greater I-V characteristic shift. Note that, since the voltages applied to the non-linear elements of both of the pixels during the non-selection period is smaller than that during the selection period, the I-V characteristic shift due to the voltages applied to the non-linear element during the non-selection period can be ignored. Therefore, when the display changes to an intermediate display, I-V characteristic of the non-linear element of pixel P2 shifts so that the non-linear element of pixel P2 develops a greater resistance when a large voltage is applied than that of pixel P1. The effective voltage applied to the liquid crystal layer during the selection period is proportional to the shaded area in FIG. 10. In the above case, it is clear that S1&gt;S2 and, as a result, pixel P2 ends up darker than pixel P1 and can be seen as an afterimage.
In this case, if a voltage applied to a non-linear element while it is displaying black is VmB and a voltage applied to a non-linear element while it is displaying white is VmW, a comparison of the effective voltages applied to each of the non-linear elements in the above display gives: EQU (1/T).intg.VmWdt&gt;(1/T).intg.VmBdt (1) EQU (white display) (black display)
where T=Ts+Th. In view of the voltage applied during the non-selection period Th which has substantially no effect on the I-V characteristic shift, the above Formula 1 can be rewritten as follows: EQU (1/Ts).intg.VmWdt&gt;(1/Ts).intg.VmBdt (2) EQU (white display) (black display)
Differences in the voltages applied to the non-linear elements during the selection period Ts generate a difference in magnitude of the I-V characteristic shift in the non-linear elements, and this leads to a difference in brightness between these two pixels that ought to exhibit the same brightness.
The afterimage described above is also generated in the case that the drive circuitry shown in FIG. 11 is used. Points at which the drive circuit of FIG. 11 differs from that of FIG. 1 are described below.
In the X driver 101, reference number 120 denotes an A/D converter for digitizing video signals which receives a video signal and generates n-bit digital data. Reference number 121 denotes a shift register that performs a shift in synchronization with the shift clock signal XSCL to sample the input digital signal. Reference number 122 denotes a latch circuit that latches and holds data that has been sampled by the shift register 121. Reference number 123 denotes an Xm drive circuit which drives the column electrode Xm by outputting a potential of either Va or -Va based on the AC inversion signal FRX for the column and the data held in the latch circuit 122.
In the Y driver 102, reference number 125 denotes a liquid crystal power generation circuit which inputs the Vp and -Vp voltages and generates the selection voltage signal Vs multiplexed in synchronization with the AC inversion signal FRY for the rows. This liquid crystal power generation circuit 125 is functionally the same as the inverter 110 of FIG. 1. The shift register 111 generates the selection signal Cn in the same way as in the configuration of FIG. 1. Reference number 112 denotes, in the same way as in FIG. 1, a power source selection switch for one cell of the drive circuitry for the row electrode Yn which drives the row electrode Yn by outputting one of Vs, Va, or -Va, based on the selection signal Cn. In this prior art example, the switching of Cn and FRY is done simultaneously, so that, when the selection signal Cn=1, an output potential of Yn=+Vp is selected when the row AC inversion signal FRY=1, and Yn=-Vp when FRY=0. However, the timing at which the selection signal Cn and the row AC inversion signal FRY switch over need not be simultaneous.
The operation of the prior art liquid crystal display device of FIG. 11 will now be described with reference to the timing chart of FIG. 12.
FIG. 12 is a timing chart of the column electrode signal Xm and the row electrode signal Yn, together with a difference signal Xm-Yn thereof. When FR (the polarity inversion signal)=0, Xm goes to -Va for an OFF level (Voff) and Va for an ON level (Von); when FR=1, Xm goes to Va for the OFF level (Voff) and -Va for the ON level (Von). The ratio of Von to Voff varies with the level of the video signal, to enable a display that includes intermediate displays obtained by pulse width modulation (PWM). The row electrode signal Yn outputs the selection voltage signal Vs during a selection period Ts, and a non-selection voltage Va or -Va during a non-selection period Th. The non-selection potential after a selection at positive potential Vp is Va, and that after a selection at negative potential -Vp is -Va.
The difference signal Xm-Yn is shown as a solid line in the signal chart at the bottom of FIG. 12. In this case, the broken-line track is that of the potential at the connection between the liquid crystal layer 113 and the non-linear element 114. Since a large voltage is applied to the non-linear element 114 during the selection period Ts, the current flowing therein is large, as can be seen from the I-V characteristic of FIG. 3, and the liquid crystal layer 113 is charged thereby. The amount of this charge is controlled by the amplitude of Xm-Yn during the selection period Ts, i.e., by the width of Von in the column electrode signal Xm. As described above, by changing the non-selection period's potential to match the polarity of the preceding selection period's potential, the signal level of the difference signal Xm-Yn is made positive in the non-selection period after a positive-polarity selection period, and negative in the non-selection period after a negative-polarity selection period. Therefore, the voltage applied to the non-linear element 114 in each non-selection period becomes small and thus it becomes difficult for the charge on the liquid crystal layer 113 to leak through the non-linear element 114 during the selection period.
The effect on the display of the I-V characteristic shift of FIG. 7 in the drive circuits of FIG. 11 will now be described. In FIG. 13, Xm1-Yn denotes the signal applied to pixel P1 of FIG. 8 and FIG. 9 and Xm2-Yn denotes the signal applied to pixel P2 thereof. A voltage VmsW applied to the non-linear element of pixel P2 during the selection period Ts of the white-display period is greater than a voltage VmsB applied to the non-linear element of pixel P1 of the black-display period, in the same manner as in FIG. 10. Thus, the non-linear element of pixel P2 has a greater I-V characteristic shift. Therefore, when the display changes to an intermediate display, I-V characteristic of the non-linear element of pixel P2 shifts to develop a greater resistance when a large voltage is applied than that of pixel P1. The effective voltage applied to the liquid crystal layer during the selection period is proportional to the shaded area in FIG. 13. It is clear that S1&gt;S2 and, as a result, pixel P2 ends up darker than pixel P1 and can be seen as an afterimage.
In both of the circuits shown in FIG. 1 and FIG. 11, if a voltage applied to a non-linear element while it is displaying black is VmB and a voltage applied to a non-linear element while it is displaying white is VmW, a comparison of the effective voltages applied to the each of the non-linear elements in the above display gives the same result as that of Formula 1. Since it is considered that the voltage applied during the non-selection period Th has substantially no effect, Formula 1 can be rewritten as the above Formula 2. Therefore, the circuitry of FIG. 11 suffers from the same problem in that differences in the voltage applied to the non-linear elements during the selection period Ts generate a difference in magnitude of the I-V characteristic shift in the non-linear elements, and this leads to a difference in brightness between non-linear elements that ought to exhibit the same brightness.